The term memory hierarchy is often used in computer architecture when discussing performance issues in computer architectural design. Traditionally, a “memory hierarchy”, in a computer storage context, distinguishes each level in the “hierarchy” by response time. Since response time, complexity, and capacity are generally related, the levels may also be distinguished by the controlling technology (e.g., transistor storage, electrically erasable programmable read-only memory, magnetic storage, optical storage, etc.).
Traditionally, a computing device has had several generalized levels within the memory hierarchy. The first and fastest level is the processor's registers and instruction/data cache close to execution units (traditionally comprised of static random access memory (SRAM)). The second and next fastest level may be a unified instruction and data cache with a size much larger than the previous level of cache. This level is usually shared among one or more CPU and other execution or processing units such as Graphics Processing Unit (GPU), Digital Signal Processing (DSP), etc. Outside integrated circuits, some or all of the main or system memory which is traditionally comprised of dynamic RAM (DRAM), may be used as cache. The next level of the memory hierarchy is often very slow compared to the prior levels. It generally comprises magnetic or solid-state memory (e.g., a hard drive or NAND flash technology, etc.) and is known as “secondary storage”. The next level is the slowest, and traditionally comprises large bulk medium (e.g., optical discs, tape back-ups, etc.).